Enciris Technologies produces high performance video processing, solutions.
As a result of our efforts we have developed and are continuing to develop a number specialized high and standard definition video processing bricks, software blocks, and board level circuitry for H.264 encoding and 4K compression among others. Presented below is a sample of our proprietary IP (Intellectual Property).
Under certain conditions we license our IP to interested customers for integration into their products. Please contact us if you would like to obtain more information about our licensing terms or have an interest in custom frame grabbers, video capture cards, video compression cards, multimedia acquisition, streaming over LAN or hardware development for low latency video compression solution based on our technology. We would be happy to help you with your project requirements.
H.264-HD Encoder Core
H.264-HD Decoder Core
A high performance HD decompression core IP that implements the H.264 (MPEG-4/AVC) video coding standard using the baseline/main/high profile up to level 5.1. Only 111.1 MHz required for 1080p at 30 fps compression for the decoding core, and 150.1 MHz for the other processing cores. Very low latency. All resolutions up to 2048x2048 and frame rates supported. Bitrates from 64 Kbps to 180 Mbps. Can be implemented in a low cost FPGA.
VC-1/WMV-HD Encoder Core
This is a high performance HD compression core IP that implements the VC-1 video coding standard using the advanced profile at level 3. Only 133MHz required for 1080p at 30fps compression Very low compression latency All resolutions and frame rates supported Large 1024x512 motion estimation search range Bitrates from 64Kbit/s to 80Mbit/s SMPTE 421M/ VC-1 Advanced profile @ level 3 Easily implemented in low cost FPGA
Multiport DDR Memory Core
An advanced multiport DDR memory controller designed to simplify the task of handling multiple data streams in and out of a DDR SDRAM. This core is especially suited to video processing or other high rate data stream systems. Optimized for LatticeECP2/MTM FPGAs Up to 16 IN ports and 16 OUT ports High DDR efficiency Easy to configure Mobile DDR, DDR1, DDR2 support 2-D transfers
Motion Estimation Core
A full featured Motion Estimation (ME) engine for high performance SMPTE-421/VC-1/WMV-HD and H.264 video encoder systems, as well as advanced deinterlacing or motion detection. 1080p30 at only 133MHz Only 540 clocks cycles per macroblock. Subpixel block matching VC-1 and H.264 compliant 1024 horizontal and 512 vertical pixel search range Optimized for true motion detection 1080p in low cost FPGAs
Video Preprocessing Core
An all-in-one high performance IP block that provides commonly needed video preprocessing functions such as deinterlacing, scaling, and color space downsampling. Deinterlacing Downscaling 4:2:2 to 4:2:0 conversion Low-Pass filtering Arbitrary video resolution HDTV applications High pixel processing rate High performance in low cost FPGA